The entire disclosure of Japanese Patent Application No. 2005-027962, filed Feb. 3, 2005 is expressly incorporated by reference herein.
1. Technical Field
The invention relates to a semiconductor device.
2. Related Art
With recent trends for higher integration and microminiaturization of semiconductor devices, higher accuracy is being called for in alignment when forming a contact layer and the like connecting wiring to a semiconductor layer. Consequently, in JP-A-8-181204, there is disclosed a technique in which an etching stopper film is provided between an interlayer insulating layer and a semiconductor layer, whereby an element and a semiconductor layer will not suffer any damage even if excessive etching is carried out when forming a contact hole.
JPA-8-181204 is an example of related art.
However, when forming an etching stopper film on a nonvolatile memory having a floating gate electrode which is an example of a semiconductor element, depending on a material of the etching stopper film, deterioration of a charge holding property may occur. Hence, even in a microminiaturized semiconductor device, development of a semiconductor device in which excellent properties have been maintained is called for.